The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
特性
Pin-compatible with the 72V261/271/281/291/2101 SuperSync FIFOs
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
5V input tolerant
Auto power down minimizes standby power consumption
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing simultaneously)
Available in the 64-pin TQFP package
Industrial temperature range (–40C to +85C) is available
产品对比
应用
文档
设计和开发
模型
ECAD 模块
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