The 5T9304I differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9304I can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 5T9304I outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

特性

  • Guaranteed low skew: 50ps (maximum)
  • Very low duty cycle distortion: 125ps (maximum)
  • Propagation delay: 1.75ns (maximum)
  • Up to 450MHz operation
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface
  • Selectable differential inputs to four LVDS outputs
  • 2.5V VDD
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

产品选择

下单器件型号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5T9304EJGI
Active TSSOP 24 I 是的 Tube
Availability
5T9304EJGI8
Active TSSOP 24 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
5T9304I Data Sheet 数据手册 PDF 241 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1606-02 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 567 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB

新闻及更多资源