The 9ZML1253E is a second generation enhanced performance DB1200ZL derivative. The part is a pin-compatible
upgrade to the 9ZML1232B, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications, while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1253E has an SMBus Write Lockout pin for increased device and system security.

特性

  • SMBus write lock feature; increases system security
  • 2 software-configurable input-to-output delay lines; manage transport delay for complex topologies
  • LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save 82mm² of area
  • 12 OE# pins; hardware control of each output
  • 3 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Selectable PLL bandwidths; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz PLL Mode; UPI support
  • 10 x 10 mm 72-VFQFPN package; small board footprint

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 72 I 是的 Tray
Availability
Active VFQFPN 72 I 是的 Reel
Availability

文档和下载

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
9ZML1233E-9ZML1253E Datasheet 数据手册 PDF 394 KB
应用指南 &白皮书
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 应用文档 PDF 244 KB
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL 应用文档 PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : TP1910-03-R1 Update the Cut-off Date Code 产品变更通告 PDF 163 KB
PCN# : TP1910-03 Top Metal Change 产品变更通告 PDF 158 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
下载
9ZML1253E IBIS Model 模型 - IBIS ZIP 21 KB
其他
PCI Express Timing Solutions Overview 概览 PDF 275 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB

开发板与套件

器件号 文档标题 类型 Company
EVK9ZXL1951D Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI 评估 Renesas