The 8A34004 System Synchronizer for IEEE 1588 generates ultra-low jitter; precision timing signals based on the IEEE 1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE).  The device can be used as a single timing and synchronization source for a system or two of them can be used as a redundant pair for improved system reliability. Digitally Controlled Oscillators (DCOs) are available to be controlled by IEEE 1588 clock recovery servo software running on an external processor. The device supports physical layer timing with Digital PLLs (DPLLs) and other timing blocks necessary to implement a Synchronous Equipment Timing Source (SETS) for SyncE. The DCOs can be controlled using IEEE 1588 information alone, or they can combine IEEE 1588 time information with physical layer frequency information from SyncE in accordance with ITU-T G.8273.2. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 Time Stamp Units (TSUs) in a system. The device supports multiple independent channels that control: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
To easily implement synchronization in IEEE 1588 systems, Renesas offers PTP Clock Manager Software for free under license.


  • Two independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 0.5Hz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • DPLLs comply with ITU-T G.8262 for Synchronous Ethernet (SyncE)
  • IEEE 1588 Support:
    • DCOs can be controlled by external IEEE 1588 software to synthesize Precision Time Protocol (PTP) / IEEE 1588 clocks with frequency resolution less than 1.11x10-16
    • Combo Bus simplifies compliance with ITU-T G.8273.2
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I2C or 50MHz SPI


文档标题 language 类型 文档格式 文件大小 日期
star 8A34004 Datasheet 数据手册 PDF 1.92 MB
8A3xxxx Firmware Version v4.8.7 Errata Notice 器件勘误表 PDF 38 KB
ClockMatrix GUI Step-by-Step User Guide 指南 PDF 10.53 MB
8A3xxxx Family Programming Guide (v4.8.7) 指南 PDF 2.35 MB
8A3xxxx Firmware Version v4.9.1 Release Notes 指南 PDF 213 KB
8A3xxxx Firmware Version v4.8.7 Release Notes 指南 PDF 143 KB
8A3xxxx Family Programming Guide (v4.8) 指南 PDF 2.35 MB
8A34xxx 48QFN EVK User Manual 手册 - 硬件 PDF 1.99 MB
AN-1010 ClockMatrix Time-to-Digital Converter 应用文档 PDF 1.92 MB
ClockMatrix™ - Channel Control for PTP with the Time of Day Counter 应用文档 PDF 393 KB
ClockMatrix Oscillator Compensation 应用文档 PDF 231 KB
Coordinating Timing Cards in Larger Systems 应用文档 PDF 349 KB
Optimizing Holdover Performance 应用文档 PDF 471 KB
Aligning 1PPS Clocks in Larger Chassis Systems 应用文档 PDF 1.62 MB
ClockMatrix: Methods for Changing DPLL Settings during a Reference Switch 应用文档 PDF 354 KB
8A3400x - Asynchronous Data Over PWM Using Timing Commander for FW4.9 应用文档 PDF 563 KB
AN-807 Recommended Crystal Oscillators for Network Synchronization 应用文档 PDF 148 KB
Mapping Clock Device Pins to Clock Numbers in the 8A34001 应用文档 PDF 390 KB
Translating Non-Integer Frequencies with ClockMatrix 应用文档 PDF 880 KB
Auto-Alignment of Outputs 应用文档 PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback 应用文档 PDF 162 KB
ClockMatrix Firmware Update through Serial Port and EEPROM v1.0 应用文档 PDF 739 KB
AN-1033 Delay Variation Measurement and Compensation 应用文档 PDF 633 KB
AN-1031 Time Alignment Background in Wireless Infrastructure 应用文档 PDF 479 KB
AN-1032 Time-of-Day Within an Ideal Chassis-Based System 应用文档 PDF 442 KB
AN-1034 Minimizing Backplane Signal Usage 应用文档 PDF 566 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment 应用文档 PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy 应用文档 PDF 659 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment 应用文档 PDF 324 KB
PCN# : 210012(R1) Firmware Update for Clock Matrix Family of Jitter Attenuators and Clock Synchronizers 产品变更通告 PDF 135 KB
PCN# : 210012 Firmware Update for Clock Matrix Family of Jitter Attenuators and Clock Synchronizers 产品变更通告 PDF 113 KB
PCN# : TP2002-01 Firmware Update from v4.8 to v4.8.7 产品变更通告 PDF 301 KB
PCN# : TP1906-05 Correct System APLL Loss-of-Lock Issue 产品变更通告 PDF 123 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN#: TP1902-02 ROM Update for ClockMatrix Products 产品变更通告 PDF 435 KB
8A3x0xx Schematic Checklist (v1.23) 其他 XLSX 318 KB
ClockMatrix Family Overview 概览 PDF 285 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB
8A3xxxx Firmware Version v4.8.8 Release Notes Release Note PDF 103 KB
8A3400x ITU-T G.8262 and G.8262.1 Compliance Test Report 报告 PDF 6.54 MB


文档标题 language 类型 文档格式 文件大小 日期
Timing Commander Personality File for ClockMatrix 8A34004 (v10.0.1, FWv4.8.7) 软件和工具 - 其他 ZIP 48.72 MB
Timing Commander Installer (v1.17) 软件和工具 - 其他 ZIP 18.02 MB
ClockMatrix Register Header Files v4.8.7 软件和工具 - 其他 ZIP 278 KB
ClockMatrix Firmware (v4.8.7) Trigger Registers, v1.1 软件和工具 - 其他 ZIP 73 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 软件和工具 - 其他 ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 软件和工具 - 其他 ZIP 177 KB
8A34004 BSDL Model 模型 - BSDL ZIP 2 KB
8A34004P BSDL Model 模型 - BSDL ZIP 2 KB
8A340xx ClockMatrix IBIS Model v1.13 模型 - IBIS ZIP 2.55 MB


Title Type Description Company
PTP Clock Manager for Linux Protocol Stack Supports IEEE 1588 and Synchronous Ethernet communication requirements. PTP Clock Manager features a clock servo and Packet Delay Variation (PDV) filter to meet the needs for G.8275.1 and G.8275.2 standards from the ITU-T. Renesas


器件号 文档标题 类型 Company
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