IDT 82V3910 is a single chip synchronous equipment timing source (SETS) for synchronous Ethernet (SyncE). The 82V3910 complies with ITU-T G.8262 for EEC-Options 1 and 2; and G.813 for SEC-Options 1 and 2; and it is suitable for SyncE, SONET and SDH equipment. Its ultra-low jitter generation makes it particularly suitable for single-board systems where the SETS directly times 10GBASE-R, 10GBASE-W, OC-192/STM-64 or 40GBASE-R PHYs.

The high-integration architecture minimizes component count and board space by including a “T0” G.8262 compliant digital PLL (DPLL); and a “T4” rate converting DPLL to provide recovered line timing to a local Building Integrated Timing Supply (BITS) or Synchronization Supply Unit (SSU). Two independent jitter attenuating analog PLLs (APLLs) are also integrated; these APLLs generate clocks with jitter below 0.3 ps RMS over the 10 kHz to 20 MHz integration range and can be used to directly time 10GbE or 40GbE network PHYs. The DPLLs lock to a wide variety of telecom and Ethernet reference frequencies and suppress incoming timing faults to generate highly-reliable output clocks for optimal network performance. The T0 DPLL can lock directly to a one pulse per second (1 PPS) reference enabling the host system to use a low-cost GPS receiver for synchronization.

IDT 82V3910 offers a solution optimized for use in Ethernet switches, routers, multiservice switching platforms, wireless backhaul equipment and other communications infrastructure. IDT 82V3910 is available in a 196-ball 15 x 15 mm CABGA package and supports standard industrial temperature range from -40degC to +85degC.
 

特性

  • Single chip solution for SyncE SETS
  • Jitter generation <0.3 ps RMS (10 kHz to 20 MHz) meets the most stringent 10G PHY requirements
  • Two ultra-low-jitter analog PLLs support three clock modes: 622.08 MHz, 625 MHz and 625 MHz x 66/64
  • Generates interface clocks (1GE, 10GBASE-R, 10GBASE-W and 40GBASE-R) and SONET/SDH (OC-192/STM-64)
  • Meets G.8262 for Synchronous Ethernet (SyncE) equipment
  • Meets Telcordia GR-253-CORE & ITU-T G.813 for SONET/SDH equipment
  • Integrates T4 DPLL and T0 DPLLs per ITU-T G.8264
  • Supports input and output clocks whose frequencies range from 1PPS to 625 MHz x 66/64
  • Internal DCO can be controlled by an external processor to be used for IEEE-1588 clock generation
  • Complemented by 82V3911 SyncE PLL for 10GbE and 40GbE
     
     

description文档

文档标题 language 类型 文档格式 文件大小 日期
star 82V3910 Shortform Datasheet 数据手册 - 简易格式 PDF 210 KB
82V3910 Datasheet 数据手册 PDF 1.00 MB
82V3910 Device Driver API Reference Manual 手册 - 软件 PDF 3.00 MB
AN-807 Recommended Crystal Oscillators for Network Synchronization 应用文档 PDF 148 KB
AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs 应用文档 PDF 300 KB
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
PCN# : A1702-01 Changed Mold Compound and Solder Paste on Select Packages 产品变更通告 PDF 93 KB
Timing Fabric for Communications Equipment Overview 概览 PDF 263 KB
82V3910 and 82V3911 Synchronous Ethernet Timing Devices 产品简述 PDF 1.34 MB

file_download下载

文档标题 language 类型 文档格式 文件大小 日期
82V3910 Device Driver Package (source only, tarball) 软件和工具 - 其他 TGZ 149 KB
82V3910 Device Driver Package (source only, zip) 软件和工具 - 其他 ZIP 243 KB