概要

This is the evaluation kit for the RC32508A jitter attenuator and clock generator.  The board comes populated with an RC32508A device.

  • Can be configured as clock generator or jitter attenuator/synchronizer
  • Low power, less than 0.8W typical
  • Low jitter, less than 50fs-RMS
  • Compliant with ITU-T G.8262 & G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter
  • Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz
  • Up to 2 independent frequency domains and 8 integer output dividers
  • Each frequency domain can be slaved with DPLL or free-run
  • DPLL can be configured as DCO
  • LVCMOS, AC-LVPECL, AC-LVDS, HCSL, AC-CML output modes supported with programmable output swing
  • Up to 2single ended or 1differential clock inputs, 1 crystal/XO/TCXO/OCXO input
  • Supports 1MHz I2C, 400kHz SMBus or 50MHz SPI serial port
  • Internal non-volatile memory (up to 8 different configurations) provides default device settings on power-up.
  • 1.8V core and output operation
  • -40° to +85°C industrial temperature operation

ドキュメント
分類 タイトル 日時
マニュアル－ハードウェア
RC32508A Evaluation Board Manual
PDF 1.84 MB
アプリケーションノート
FemtoClock 2 – Generating Synchronous Ethernet (SyncE) Clocks
PDF 377 KB
マニュアル－ソフトウェア
FemtoClock®2 GUI User Guide
PDF 1.22 MB
ガイド
FemtoClock2 Debug Guide
PDF 80 KB
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設計・開発

ソフトウェア／ツール
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    Processing table
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    Lab on the Cloud Demo for FemtoClock®2 Ultra-Low Phase Noise Synthesizer and Jitter Attenuator

    Demonstration of Renesas’ Lab on the Cloud virtual environment for FemtoClock®2 ultra-low phase noise synthesizer and jitter attenuator.

    Video List
    Lab on the Cloud Demo for FemtoClock®2 Ultra-Low Phase Noise Synthesizer and Jitter Attenuator