クロック&タイミング

概要

The ICS8543-09 is a low skew, high performance1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543-09 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8543-09 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
 
Guaranteed output and part-to-part skew characteristics make the ICS8543-09 ideal for those applications demanding well defined performance and repeatability.
8543-09 Block Diagram
8543-09 - Pin Assignment
8543-09 Block Diagram
8543-09 - Pin Assignment
  • Four differential LVDS output pairs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential
    input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • PCLK, nPCLK supports the following input types:
    LVPECL, CML, SSTL
  • Maximum output frequency: 800MHz
  • Translates any single-ended input signal to LVDS levels with
    resistor bias on nCLK input
  • Additive phase jitter, RMS: 0.146ps (typical)
  • Output skew: 100ps (maximum)
  • Part-to-part skew: 700ps (maximum)
  • Propagation delay: 3.3ns (maximum)
  • Full 3.3V supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • Industrial temperature information available upon request

ドキュメント

タイトル 分類 日付
8543-09 Data Sheet
PDF1.23 MB
データシート
AN-805 Recommended Ferrite Beads
PDF91 KB
アプリケーションノート
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
アプリケーションノート
AN-828 Termination - LVPECL
PDF322 KB
アプリケーションノート
AN-844 Termination - AC Coupling Clock Receivers
PDF170 KB
アプリケーションノート
AN-846 Termination - LVDS
PDF133 KB
アプリケーションノート
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
アプリケーションノート
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
アプリケーションノート
AN-833 Differential Input Self Oscillation Prevention
PDF180 KB
アプリケーションノート
AN-834 Hot-Swap Recommendations
PDF153 KB
アプリケーションノート
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
アプリケーションノート
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
アプリケーションノート
AN-815 Understanding Jitter Units
PDF565 KB
アプリケーションノート
PDN# : TP-20-05(R1) Revised PDN - Change Replacement for 85411AMLF(T) from 5PB1102CMGI(8) to 8SLVP1102ANLGI(8)
PDF743 KB
EOL通知
PDN# : TP-20-05 End-of-Life (EOL) Process on Select Part Numbers
PDF715 KB
EOL通知
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE
PDF363 KB
EOL通知
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE
PDF209 KB
EOL通知
Clock Distribution Overview
PDF217 KB
概要
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly
PDF611 KB
製品変更通知
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly
PDF611 KB
製品変更通知
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location
PDF596 KB
製品変更通知
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location
PDF544 KB
製品変更通知
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages
PDF95 KB
製品変更通知
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages
PDF50 KB
製品変更通知
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products
PDF361 KB
製品変更通知

設計・開発

ソフトウェアダウンロード

タイトル 分類 日付
PDN# : TP-20-05(R1) Revised PDN - Change Replacement for 85411AMLF(T) from 5PB1102CMGI(8) to 8SLVP1102ANLGI(8)
PDF743 KB
EOL通知
PDN# : TP-20-05 End-of-Life (EOL) Process on Select Part Numbers
PDF715 KB
EOL通知
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE
PDF363 KB
EOL通知
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE
PDF209 KB
EOL通知

ECADモデル

[製品選択]テーブル内の製品名をクリックするとSamacSysが提供する回路図シンボル、PCBフットプリント、3D CADモデルがご確認いただけます。 お探しのシンボルやモデルが見つからない場合、Webサイトから直接リクエストできます。

ECADモデルを調べる

製品選択

    Processing table
    型名
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    8543AG-09LF
    block_flippedEOL品
    memory
    view_in_ar
    		TSSOP 20 C Yes Tube
    8543AG-09LFT
    block_flippedEOL品
    memory
    view_in_ar
    		TSSOP 20 C Yes Reel
    Parametric Table tips

    Tips for Using This Parametric Table:

    • Hide Filters button in header: Collapse or expands filters
    • Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
    • Reset button in header: Reset all filters to the page default
    • Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
    • Export button in header: Export the filtered results of the table to an Excel document
    • Filter parts search bar in header: Type to filter table results by part number
    • Hide column button in column headers: Select to hide columns in table
    • AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
    • Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
    • Document icon next to product name in row: View the featured document for this product
    • Chip icon next to the right of the document icon in row: View the block diagram for this product
    • Cart icon to the right of the chip icon: Indicates that samples are available for this product