概要

The 9ZXL0853E is a Gen1–5  compliant, enhanced performance differential clock buffer. The device supports complex clocking architectures like SRIS and SRNS. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0853E has an SMBus Write Lock feature for increased device and system security. The device also features up to 9 selectable SMBus addresses.
 
  • PCIe Gen1–5 compliance
  • SMBus Write Protect feature; increase system security
  • UPI/QPI support
  • Supports PCIe SRIS and SNRS clocking  
  • LP-HCSL outputs with 85Ω Zout; eliminate 4 resistors per output pair
  • 8 OE# pins; hardware control of each output
  • 9 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz ZDB mode
  • 6 × 6 mm 48-VFQFPN package; small board footprint
 

ドキュメント

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データシート
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アプリケーションノート
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概要
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概要
 

設計・開発

ボード&キット

モデル

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ビデオ&トレーニング

PCIe Gen5 Clock Buffers

Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page