Zynq UltraScale+ MPSoC reference design set up for always-on and optimized for PL performance.
Rail | Voltage | Power Supply Rails |
---|---|---|
Rail 1 | 0.85/0.9V | VCCINT, VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR, VCCINT_VCU, VCCINT_IO, VCCBRAM |
Rail 2* | 1.8V* | VCC_PSAUX, VCCAUX, VCCAUX_IO, VCC_PSDDR_PLL, VCCADC, VCC_PSADC |
Rail 3* | 1.2V* | VMGTAVTT (GTH), VMGTYAVTT (GTY), VCC_PSPLL |
Rail 4 | 1.1-1.5V | VCCO_PSDDR |
Rail 5 | 1.8-3.3V | VCCO_PSIO |
Rail 6* | 1.8V* | VMGTVCCAUX (GTH), VMGTYVCCAUX (GTY), VPS_MGTRAVTT |
Rail 7* | 0.9V* | VMGTAVCC (GTH), VMGTYAVCC (GTY), VPS_MGTRAVCC |
Rail 8 | 1.2-3.3V | HDIO_VCCO |
Rail 9 | 1-1.8V | HPIO_VCCO |
* Please see the Xilinx UltraScale Architecture PCB Design User Guide for additional rail specifications.