Overview

Zynq UltraScale+ MPSoC reference design set up for full power management flexibility.

Features

  • Independent control of the different power domains for access to low power (~mW) states, e.g. battery-powered app
  • Large number of independent rails; Applicable to all speed grades
Full Power Domain Flexibility Consolidation
Full Power Domain Flexibility Consolidation
Rail Voltage Power Supply Rails
Rail 1 0.85V VCC_PSINTLP
Rail 2 1.8V VCC_PSAUX, VCC_PSADC
Rail 3* 1.2V* VCC_PSPLL
Rail 4 1.8-3.3V VCCO_PSIO
Rail 5 0.85/0.9V VCC_PSINTFP, VCC_PSINTFP_DDR
Rail 6* 1.8V* VCC_PSDDR_PLL
Rail 7 1.1-1.5V VCCO_PSDDR
Rail 8* 0.85V VCCINT_VCU, VCCINT, VCCINT_I, VCBRAM
Rail 9* 1.8V VCCAUX, VCCAUX_IO, VCCADC, DDR_VPP1
Rail 10* 0.85V* VPS_MGTRAVCC
Rail 11* 1.8V* VPS_MGTRAVTT
Rail 12* 1.2V VMGTAVTT (GTH), VMGTYAVTT (GTY)
Rail 13* 0.9V VMGTAVCC (GTH), VMGTYAVCC (GTY)
Rail 14* 1.8V VMGTVCCAUX (GTH), VMGTYVCCAUX (GTY)
Rail 16 1.2-3.3V HDIO_VCCO
Rail 17 1-1.8V HPIO_VCCO

* Please see the Xilinx UltraScale Architecture PCB Design User Guide for additional rail specifications.

 

Use Case 4.1 for ZU2 – ZU3

High Load Rails

  • Rail 5 = 2.15-2.75A
  • Rail 8 = 3.6-4.6A

Reference Design Files

Recommended Parts

Zynq UltraScale+ MPSoC Use Case 4.1

Use Case 4.2 for ZU4 – ZU5

High Load Rails

  • Rail 5 = 2.15-2.75A
  • Rail 8 = 7.4-12.1A

Reference Design Files

Recommended Parts

Zynq UltraScale+ MPSoC Use Case 4.2

Use Case 4.3 for ZU6 – ZU9

High Load Rails

  • Rail 5 = 2.15-2.75A
  • Rail 8 = 15.7-20.8A
  • Rail 12 = 2.05A
  • Rail 13 = 2A

Reference Design Files

Recommended Parts

Zynq UltraScale+ MPSoC Use Case 4.3

Use Case 4.4 for ZU11 – ZU19

High Load Rails

  • Rail 5 = 2.75A
  • Rail 8 = 23—32.2A
  • Rail 12 = 2.5-10.5A
  • Rail 13 = 2.5-7.5A

Reference Design Files

Recommended Parts

Zynq UltraScale+ MPSoC Use Case 4.4