W 00 1F 00
W 00 00 C4 -- activate spi 3w; 
W 00 01 05 -- disable NCO & SSBM (^2 interpolation)
W 00 02 00 -- dacclk 2xclkin
W 00 13 88 -- H3 improvement
W 00 14 88 -- H3 improvement
W 00 11 0A -- H2 improvement

W 00 1F 04
W 00 07 E2 -- choose ILA initialization at 4th /A/ with no scrambling


#W 00 0D 0A -- polarity of lane 3 and lane 1

W 00 1B F0 -- error handling

W 00 1F 02

W 00 00 30 -- full re-init; sync starts at '1'


