W 00 1F 00
W 00 00 44 -- activate spi 4w; 
W 00 01 03 
W 00 02 10 -- pll_8x
W 00 0C 00 -- 2 DAC
W 00 0F 01 -- NS enabled
W 00 13 88 -- H3 improvement
W 00 14 88 -- H3 improvement
W 00 11 0A -- H2 improvement
W 00 1B 80
W 00 1D 80
W 00 1F 04
W 00 07 E2 
W 00 0D 0F
W 00 1F 02
W 00 03 22 -- define jclk_cntrl (cdi; fclk_sel)
W 00 00 30 -- full re-init; sync starts at '1'
