W 00 1F 00
W 00 00 44 -- activate spi 4w; 
W 00 01 02 -- ^4 interpolation
W 00 02 80 -- pll_bypass
W 00 13 88 -- H3 improvement
W 00 14 88 -- H3 improvement
W 00 11 0A -- H2 improvement
W 00 1F 04
W 00 07 E3 -- choose ILA initialization at 4th /A/
W 00 08 02 -- dynamic re-alignment
W 00 1C 0F -- (re)sync_over_link
W 00 1F 01
W 00 00 05 -- mds_(eq_check[1:0],run,nco,sel_ln32,32T_ena,master,ena)
W 00 01 3F -- mds_win_period_a[7:0]
W 00 02 1F -- mds_win_period_b[7:0]
W 00 03 10 -- mds_(eval_ena,prerun_ena,pulsewidth[2:0])
W 00 04 40 -- mds_(man,man_adjustdly[6:0])
W 00 05 FF -- mds_auto_cycles[7:0]
W 00 06 18 -- mds_(sr[2:0],relock,lock_cnt[3:0])
W 00 1F 02
W 00 03 11 -- define jclk_cntrl (cdi; fclk_sel)
W 00 06 0F -- re-adjust dcsmu-timer (tweak startup-time)
W 00 00 30 -- full re-init; sync starts at '1'
