W 00 1F 00
W 00 00 44 -- activate spi 4w; 
W 00 01 85 -- enable NCO & SSBM (^2 interpolation)
W 00 02 80 -- PLL by-pass ; dac-phase set to 0 degrees
W 00 03 7B -- NCO[ 7:0 ]
W 00 04 58 -- NCO[15:8 ]
W 00 05 2C -- NCO[23:16]
W 00 06 35 -- Fnco = FDAC/4,81
W 00 0F 01 -- NS enabled
W 00 15 00 -- sel_ph_fine = 0  
W 00 13 88 -- H3 improvement
W 00 14 88 -- H3 improvement
W 00 11 0A -- H2 improvement
W 00 1F 04
W 00 07 E3 -- choose ILA initialization at 4th /A/
W 00 1F 02
W 00 00 30 -- full re-init; sync starts at '1'
