W 00 1F 00
W 00 00 44 -- activate spi 4w; 
W 00 01 85 -- nco, ssbm-mode=001, 2^
W 00 02 01 -- inverse clock-edge
W 00 03 99 -- nco[ 7:0 ]
W 00 04 99 -- nco[15:8 ]
W 00 05 99 -- nco[23:16]
W 00 06 01 -- nco[31:24]
W 00 11 0C -- adjust dac_dig_bias (H2-improvement)
W 00 14 6E -- adjust dac_cas_bias (H3-improvement)
W 00 1F 02
W 00 0A 50 -- insert IQ DC-levels
W 00 0D 20 -- "00" & I_dc_level[13:8]
W 00 0F 00 -- "00" & Q_dc_level[13:8]
W 00 1F 04
W 00 07 E3 -- choose ILA initialization at 4th /A/
W 00 1C 0F -- (re)sync_over_link
W 00 1F 01
W 00 00 17 -- mds_(eq_check[1:0],run,nco,sel_ln32,32T_ena,master,ena)
W 00 01 67 -- mds_win_period_a[7:0]
W 00 02 44 -- mds_win_period_b[7:0]
W 00 03 13 -- mds_(eval_ena,prerun_ena,pulsewidth[2:0])
W 00 04 40 -- mds_(man,man_adjustdly[6:0])
W 00 05 40 -- mds_auto_cycles[7:0]
W 00 1F 02
W 00 00 30 -- full re-init; sync starts at '1'
