The 5P49V6968 is a member of IDT's VersaClock® 6E programmable clock generator family. The 5P49V6968 is intended for high-performance consumer, networking, industrial, computing, and data-communications applications. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation.
Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface.


  • < 100mW core power (at 3.3V)
  • < 0.5ps RMS phase jitter (typical)
  • PCIe Gen 1/2/3/4/5 spread spectrum off
  • PCIe Gen 1/2/3/4 spread spectrum on
  • 1/10GbE, USB 3.0
  • 3 universal outputs pairs: LVPECL, LVDS, HCSL, or 6 LVCMOS outputs
  • 3 independent frequencies with 0.001MHz–350MHz output range
  • 8 additional copies of LP-HCSL outputs (1 independent frequency)
  • Reference output
  • 1.8V / 2.5V / 3.3V core and output voltages
  • 2 programmable I²C addresses allowing multiple devices to be used in same system
  • Up to 4 different configuration sets in OTP non-volatile memory
  • Supported by IDT Timing Commander™  software tool
  • Quick sampling and customization process supported by online-form submission
  • 6 x 6 mm 48-VFQFPN package
  • -40°C to +85°C operating temperature range


5P49V6968 5P49V6965 5P49V6967 5P49V6975
Inputs (#) 2 2 2 1
Outputs (#) 11 5 9 5
Phase Jitter Typ RMS (ps) 0.500 0.500 0.500 0.500


文档标题 language 类型 文档格式 文件大小 日期
star 5P49V6968 Datasheet 数据手册 PDF 1.08 MB
IDT Products for Wired Broadband Applications Application Brief PDF 686 KB
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output 应用文档 PDF 256 KB
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter 应用文档 PDF 486 KB
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-970 Glitchless Frequency Adjustment using Fractional Output Divider 应用文档 PDF 717 KB
AN-954 Layout and EMI Recommendations for Automotive Applications 应用文档 PDF 406 KB
AN-960 Layout and EMI Recommendations for Automotive Applications (short form) 应用文档 PDF 342 KB
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products 应用文档 PDF 901 KB
AN-918 Programmable Clocks vs Crystal Oscillators 应用文档 PDF 307 KB
AN-905 Using VersaClock® 6 as Reference Clock for Xilinx® Series 7 FPGAs 应用文档 PDF 188 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
Timing Commander Installation Guide 指南 PDF 497 KB
VersaClock 6E Family Register Descriptions and Programming Guide 手册 - 开发工具 PDF 872 KB
PCI Express Timing Solutions Overview 概览 PDF 275 KB
VersaClock Family Overview 概览 PDF 376 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB
PCN# : 210023 Add Alternate Assembly Locations on Select VFQFN Packages 产品变更通告 PDF 726 KB
IDT Clocks for Xilinx Ultrascale FPGAs 技术摘要 PDF 256 KB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs 技术摘要 PDF 238 KB


文档标题 language 类型 文档格式 文件大小 日期
VersaClock 6E Timing Commander Personality File v1.4.0 软件和工具 - 其他 ZIP 13.96 MB
Timing Commander Installer (v1.17) 软件和工具 - 其他 ZIP 18.02 MB


器件号 文档标题 类型 Company
5P49V6968-EVK Evaluation Board for 5P49V6968 VersaClock® 6E 评估 Renesas