The 8430S10I-02 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN30XX/CN31XX/CN38XX/CN58XX processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the 8430S10I-02 supports telecommunication, networking, and storage requirements.

特性

  • One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels
  • Nine LVCMOS/ LVTTL outputs, 20Ω typical output impedance
  • Selectable external crystal or differential (single-ended) input source
  • Crystal oscillator interface designed for 25MHz, parallel resonant crystal
  • Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, SSTL input levels
  • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
  • Power output supply modes LVDS and LVPECL - full 3.3V LVCMOS - full 3.3V or mixed 3.3V core/2.5V output
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8430S10BYI-02LF
Active PTQFP 48 I 是的 Tray
Availability
8430S10BYI-02LFT
Active PTQFP 48 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8430S10I-02 Datasheet 数据手册 PDF 732 KB
Errata# NEN-10-09 勘误表 PDF 61 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products 应用文档 PDF 128 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
Netcom LVCMOS Power Dissipation 应用文档 PDF 469 KB
Netcom LVCMOS Driver Termination 应用文档 PDF 218 KB
PCN / PDN
PCN# : A1709-02 Add alternate assembly at OSET and Convert to Copper Wire 产品变更通告 PDF 35 KB
PCN# : A1402-02 Alternate Assembly Locations 产品变更通告 PDF 34 KB
下载
8430S10I-02 IBIS Model 模型 - IBIS ZIP 116 KB
其他
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB