概览

简介

The 651S is a low cost, high-speed single input to four output LVCMOS clock buffer. The 651S has best in class Additive Phase Jitter of sub 50 fsec.

特性

  • Low additive phase jitter RMS: 50 fs
  • Extremely low skew outputs (50 ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and 8-pin DFN, Pb-free
  • Input / Output clock frequency up to 200 MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating Voltages: 1.8 V to 3.3 V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

产品对比

应用

文档

类型 文档标题 日期
数据手册 PDF 305 KB
应用文档 PDF 187 KB
概览 PDF 217 KB
产品变更通告 PDF 268 KB
产品变更通告 PDF 611 KB
产品变更通告 PDF 611 KB
应用文档 PDF 495 KB
应用文档 PDF 442 KB
应用文档 PDF 565 KB
9 items

设计和开发

模型

Low-jitter LVCMOS Fanout Clock Buffers by IDT