IDT’s JEDEC-compliant 4RCD0124K is a Gen 1 DDR4 registered clock driver (RDC) for Enterprise Class Server RDIMMs, LRDIMMs and UDIMMs operating with a 1.2V Vdd supply. It features a 32-bit 1:2 register command, address buffer with parity designed for 1.2V VDD operation.

特長

  • JEDEC Compliant RCD  
  • DDR4-1600/1866/2133/2400
  • Optimized for JEDEC DDR4 2400 MT/s RDIMM, LRDIMM and UDIMM
  • Designed to be used with IDT 4DB0226KA (DDR4 DB) and IDT TSE2004GB2 (DDR4 Temperature Sensor)
  • Supports CKE Power Down operation modes
  • Support Quad Chip Select Operation
    • Direct Dual CS Mode
    • Direct QuadCS Mode
  • Encoded QuadCS Mode
  • Pinout optimized DDR4 RDIMM, LRDIMM and UDIMM PCB layout
  • Provides access to internal control words for configuring the device features and adapting in different RDIMM and system applications
  • Available in 253-ball Dual-Pitch (0.50mm/0.65mm), 15 x 20 Grid , Rectangular Ball Grid Array Package

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
アプリケーションノート、ホワイトペーパー
IDT DDR4 LRDIMMs Let You Have It All 简体中文 ホワイトペーパー PDF 1.08 MB
DDR4 LRDIMMs For Both Memory Capacity and Speed ホワイトペーパー PDF 5.22 MB
PCN / PDN
PCN# : A1911-01 Adding 2D barcode on product marking 製品変更通知 PDF 493 KB
PCN# A1901-01 : Assembly Sample Open/Short Test Introduced at Amkor and Stats Chippac, Korea 製品変更通知 PDF 208 KB
PCN# : A1903-01 Add alternate bump location and Transfer Assembly Location 製品変更通知 PDF 294 KB
PCN# : A1902-03 Add ASECL as an alternate assembly facility. 製品変更通知 PDF 246 KB
PCN# : A1706-01 (R2) Change in Bumping Location on Select Packages 製品変更通知 PDF 78 KB
PCN# : A1706-01 (R1) Change in Bumping Location on Select Packages 製品変更通知 PDF 77 KB
PCN# : A1706-01 Change in Bumping Location on Select Packages 製品変更通知 PDF 32 KB
PCN# : A1409-02 Alternate Bump and Assembly Location FCCSP-253 製品変更通知 PDF 25 KB
PCN# : TB1407-02 Alternate Test and Backend Location 製品変更通知 PDF 22 KB
その他資料
star Memory Interface Products Family Overview 概要 PDF 515 KB