The 5PB1110 is a high-performance 1:10 LVCMOS clock buffer. It has best-in-class Additive Phase Jitter of 50 fsec RMS.
 
The 5PB1110 also supports an Output Enable function. It is available in 20-pin QFN and TSSOP packages and can operate from a 1.8 V to 3.3 V supply.
 

特長

  • High performance 1:10 LVCMOS clock buffer
  • Very low pin-to-pin skew <50 ps
  • Very low additive jitter <50 fs
  • Supply voltage: 1.8 V to 3.3 V
  • fmax = 200 MHz
  • Integrated serial termination for 50ohm channel
  • Packaged in 20-pin TSSOP and small QFN packages
  • Extended (-40°C to +105°C) temperature range
  • AEC-Q100 qualified, Automotive Grade 2 (-40°C to +105°C)

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
star 5PB11xx Family Datasheet データシート PDF 430 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
PCN# : TB1912-02(R1) Convert Shipping Media from Tube or Tray to Cut Reel 製品変更通知 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media from Tube or Tray to Cut Reel 製品変更通知 PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
PCN# : A1711-01 Add ASECL as Alternate Assembly for Select Devices 製品変更通知 PDF 30 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 製品変更通知 PDF 583 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
PCN# : TB1503-01R1 Carrier Tape Standardization for Selective Packages 製品変更通知 PDF 333 KB
PCN# : TB1503-01 Carrier Tape Standardization for Selective Packages 製品変更通知 PDF 291 KB
Clock Distribution Overview 概要 PDF 217 KB
IDT Ultra-Low-Jitter Single-Ended Buffer Family Overview 概要 PDF 252 KB
IDT Clock Generation Overview 概要 PDF 1.83 MB

file_downloadダウンロード

タイトル language 分類 形式 サイズ 日付
5PB11xx Family IBIS Model モデル-IBIS ZIP 24 KB