The 82V3203A is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. An input clock is automatically or manually selected for DPLL locking. The DPLL supports three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed only through an I2C programming interface.
Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
Limits the phase and frequency offset of the outputs
Supports manual and automatic selected input clock switch
Supports automatic hitless selected input clock switch on clock failure
Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
Provides three 2 kHz, 4 kHz or 8 kHz frame sync input signals, and a 2 kHz and an 8 kHz frame sync output signals
Provides three input clocks whose frequency cover from 2 kHz to 155.52 MHz
Provides two output clocks whose frequency cover from 1 Hz to 622.08 MHz
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports CMOS input/output and PECL/LVDS output technologies