The ISL70005SEH is radiation hardened dual output Point-of-Load (POL) regulator combining the high efficiency of a synchronous buck regulator with the low noise of a Low Dropout (LDO) regulator. They are suited for systems with 3.3V or 5V power buses and can support continuous output load currents of 3A for the buck regulator and ±1A for the LDO.
The buck regulator uses a voltage mode control architecture and switches at a resistor adjustable frequency of 100kHz to 1MHz. Externally adjustable loop compensation allows for an optimum balance between stability and output dynamic performance. The internal synchronous power switches are optimized for high efficiency and excellent thermal performance.
The LDO is completely configurable independent of the switching regulator. It uses NMOS pass devices and separate chip bias voltage (L_VCC) to drive its gate, enabling the LDO to operate with a very low voltage at the L_VIN input. The LDO can sink and source up to 1A continuously, making it an ideal choice to power DDR memory.
The ISL70005SEH is available in a space saving 28 Ld ceramic dual flat-pack package or in die form. It is specified to operate across a temperature range of TA = -55°C to +125°C.
- Dual output regulator: Sync buck and LDO
- Independent EN, SS, and PG indicators
- ±1% reference voltage
- 1A current sourcing/sinking capability on LDO
- External clock synchronization: 100kHz to 1MHz
- Full military temperature range operation
- TA = -55°C to +125°C
- TJ = -55°C to +150°C
- Radiation acceptance testing - ISL70005SEH
- HDR (50-300rad(Si)/s): 100krad(Si)
- LDR (0.01rad(Si)/s): 75krad(Si)
- SEE hardness (see test report)
- No SEB or SEL at LET 86.4MeV•cm2/mg
- SET at LET 86.4MeV•cm2/mg <±3% ΔVOUT
- No SEFI at LET 43MeV•cm2/mg
- Electrically screened to DLA SMD 5962-19209
- Point-of-load for low power FPGA core, auxiliary and I/O supply voltages
- DDR memory power for VDDQ and VTT rails
- Distributed power system of satellite payloads