The V850ES/JG3-L is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, USB function controller and enables an extremely high cost-performance for applications that require USB function controller, such as PC peripheral device, ECR peripheral device, and industrial instrument.


Key Features:

  • Operating Voltage: 2.0 to 3.6 V (2.5 MHz), 2.2 to 3.6 V (5 MHz), 2.7 to 3.6 V (20 MHz), 3.0 to 3.6 V (USB operating)
  • Max. frequency: 20 MHz
  • ROM capacities: 256 KB to 1 MB flash memory
  • RAM capacities: 40 KB to 80 KB
  • Package: 100-pin plastic LQFP package, 121-pin plastic FBGA package
  • Minimum instruction execution time:
    • 50 ns (operating on main clock (fXX) of 20 MHz: VDD = 2.7 to 3.6 V) (In PLL mode: x 4 : 5 MHz) - 62.5 ns (operating on main clock (fXX) of 16 MHz: VDD = 3.0 to 3.6 V) (In PLL mode: x 8, 1/3 : 6 MHz) - 200 ns (operating on main clock (fXX) of 5 MHz: VDD
  • General-purpose registers: 32 bits x 32 registers
  • CPU features:
    • Signed multiplication (16 x 16 -> 32): 1 to 2 clocks
    • Signed multiplication (32 x 32 -> 64): 1 to 5 clocks
    • Saturated operations (overflow and underflow detection functions included)
    • 32-bit shift instruction: 1 clock
    • bit manipulation instructions
    • Load/store instructions with long/short format
  • Memory space:
    • 64 MB of linear address space (for programs and data)
    • External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM)
  • Interrupts and exceptions:
    • Non-maskable interrupts: 2 sources
    • Maskable interrupts: 62 sources
    • Software exceptions: 32 sources
    • Exception trap: 2 sources
  • I/O ports: 80
  • Timer function:
    • 16-bit interval timer M (TMM): 1 channel
    • 16-bit timer/event counter P (TMP): 6 channels
    • 16-bit timer/event counter Q (TMQ): 1 channel
    • Watch timer: 1 channel
    • Watchdog timer 2: 1 channel
  • Serial interface:
  • Asynchronous serial interface A (UARTA), 3-wire variable-length serial interface B (CSIB), I2C bus interface (I2C)
    • UARTA/CSIB: 1 channel
    • UARTA/I2C: 2 channels
    • CSIB/I2C: 1 channel
    • CSIB: 3 channels
    • UARTA: 3 channels
    • UARTC: 1 channel
    • USB function: 1 channel
  • A/D converter: 10-bit resolution: 12 channels
  • D/A converter: 8-bit resolution: 2 channels
  • DMA controller: 4 channels
  • DCU (Debug control unit): JTAG interface
  • Clock generator:
    • During main clock or subclock operation
    • 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
    • clock-through mode/PLL mode selectable
    • Internal oscillation clock: 220 kHz (TYP.)
  • Power-save functions: HALT/IDLE1/IDLE2/STOP/low-voltage STOP/subclock/sub-IDLE/low-voltage subclock/low-voltage sub-IDLE mode/RTC backup mode


Pin count – Memory size Lineup:

Program Flash

Below you will find information to support the development of your application.
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Resources for Software and Hardware

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Software Design Support

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CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
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