The V850E/PHO3 devices provide an excellent combination of general purpose peripheral functions like serial communication interfaces, timers/counters, measurement and control functions, with dedicated motor control timers and full CAN network support. The integrated FlexRay™ interface implements the FlexRay™ network protocol and ideally suited for automotive control and electric power steering (EPS) applications. It is also an excellent choice for other applications where a combination of sophisticated peripheral functions and CAN network support is required.


Main Solutions

Key Features:

  • Operating voltage: 3.3 V ± 0.3 V, 1.5V ± 0.15 V (refer to Data Sheet)
  • Max. frequency: 128 MHz
  • ROM capacitties: μPD70F3483: 768 KB, μPD70F3441: 992 KB
  • RAM capacities: 60 KB
  • Data Flash: 32 KB
  • Package: 357 pin BGA (0.8 mm ball pitch)
  • CPU
    • V850E (32-bit RISC)
    • Floating-point arithmetic unit (single precision, according to IEEE 754-85 standard)
  • Internal memory
  • External memory interface
    • Address bus: 22 bit
    • Data bus: sizeable 32, 16, 8 bit
    • Features: Four programmable chip select areas, Wait state insertion function,  Idle state insertion function,  Endian switch function
  • Operating clocks
    • CPU frequency: max. 128 MHz
    • MainOSC: operates on 16 MHz crystal
    • PLL ratio: x 8, x 5
    • Internal oscillator: 6.8 MHz typ.
    • FlexRay: 80 MHz
  • Interrupts
    • Non-maskable: 1 ch
    • Maskable int.: 101 ch
    • Maskable ext.: 14 ch
  • I/O lines
    • I/O ports: 143
    • Input ports: 5
  • Timers
    • TAA: 10 ch (16-bit general purpose timer/counter, cascadable for 32-bit operations)
    • TMS:  2 ch (16-bit timer/counter with Motor Control Functions)
    • TMT:  2 ch (16-bit general purpose timer/counter with PWM functions)
  • A/D converters
    • Analog inputs: 20
    • Resolution: 10 bit
    • Type: Successive approximation
  • Serial interfaces
    • UARTC 3 ch
    • CSIB 2 ch Clocked Serial Interface
    • CSIE 2 ch queued CSI
    • CAN: 2 ch CAN (32 message buffers for each channel)
  • FlexRay: 2 ch (Protocol specification V2.1)
  • DMA: 8 ch
  • Boundary scan: provided
  • Other functions
    • Power save modes: HALT
    • RNG: Random Number Generator provided
    • Clock Monitor: Main oscillator Monitor provided
    • Aux. frequency output: Programmable baud rate Generator provided
    • On-chip debug:
    • Connection of an external N-Wire emulator provided NBD (Non Break Debug) interface with 4 KB of tuning RAM (overlay RAM) for RAM monitoring,  data tuning, calibration and bypassing


Pin count – Memory size Lineup:

Program Flash

Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.

Resources for Software and Hardware

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Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)
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