Ideal for the motor control for HEV/EV. The high-end in-vehicle microcomputer of resolver / one digital converter loading
The RH850/C1M with internal Resolver/Digital Converter (RDC2) and motor control unit (EMU2) reduce CPU load and can control motors with very little CPU interaction.
Main Solutions
Key Features:
| ITEM | RH850/C1M | |
|---|---|---|
| Part Name | R7F701271EAFP | |
| CPU | CPU system | RH850G3M (With Lockstep) |
| CPU frequency | 240 MHz | |
| Internal peripheral guard function (IPG) | Supported | |
| System error notification function (SEG) | Supported | |
| Memory protection unit (MPU) | Supported | |
| Floating point unit (FPU) | Supported | |
| Memory | Program Flash | 2 MB |
| Instruction cache | 8 KB | |
| Local RAM | 64 KB | |
| Data Flash | 32 KB | |
| Global RAM | 64 KB | |
| External Interrupt | Maskable interrupt (IRQ) | 8 |
| Non maskable interrupt (NMI) | 1 | |
| DMA, DTS | DMA 16 channels, DTS 128 channels | |
| Clock | Main oscillator (Main OSC) | 20 MHz |
| PLL | Supported | |
| Security | ICU-S was removed | |
| I/O ports | 66 | |
| Timers | Timer array unit J (TAUJ) | 1 unit (4 timers / unit) |
| Motor control timers (TSG3) | 2 units | |
| Timer option (TAPA) | 4 units | |
| Timer pattern buffer (TPBA) | 1 unit | |
| Timers for operating system (OSTM) | 2 units | |
| Encoder timers (ENCA) | 2 units | |
| Watchdog timer (WDTA) | 1 unit | |
| Serial interfaces | Clocked serial interface (CSIH) | 2 channels |
| CAN interface (RS-CAN) | 4 channels (total 256 message buffers) | |
| Serial communication interface (SCI3) | 3 channels | |
| A/D converter | 12-bit A/D converter core | 2 units |
| ADCC0 (Input pin count and Track and Hold count) | 10 input pins x 6 Track and Hold | |
| ADCC1 (Input pin count and Track and Hold count) | 15 input pins x 6 Track and Hold | |
| Motor control | Resolver/Digital Converter (RDC2) | 1 unit |
| Enhanced motor control unit (EMU2) | 1 unit (2 channels) | |
| Other functions | Error control module (ECM), Clock monitor (CLMA), Data CRC (DCRA) 2 units, Error collection coding (ECC), On-chip debug (OCD), Peripheral interconnection 1 (PIC1A) 1unit and Peripheral interconnection 2 (PIC2B) 1 unit | |
| Power supply voltage | Internal | 1.25 ± 0.1 V, 3.3 ± 0.3 V |
| For I/O | 5.0 ± 0.5 V | |
| For Resolver/Digital converter | 5.0 ± 0.5 V | |
| For A/D converter | 5.0 ± 0.5 V | |
| Operating temperature | Junction temperature (Tj) | -40 to 150 ℃ |
| Package | 144-pin QFP (20 x 20 mm) | |
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Software Design Support
| Title | Description | |||
|---|---|---|---|---|
| CS+ | An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.) | |||
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| E1 | A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.) | |||
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