The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.
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Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
Buy / Sample |
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Part Number | ||||||||
9DB633AGILF circleActive Samples Available |
TSSOP | 28 | I | Yes | Tube | 1 | Get Samples, | |
TSSOP | 28 | I | Yes | Reel | 1 | |||
9DB633AGLF circleActive Samples Available |
TSSOP | 28 | C | Yes | Tube | 1 | 5.158 | Get Samples, |
TSSOP | 28 | C | Yes | Reel | 1 |