Overview

Description

The M2004 variants -02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation in a high-speed data communications system. The clock multiplication ratio and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response. The M2004-12 adds Hitless Switching with Phase Build-out (HS/PBO) to ensure that reference clock reselection does not disrupt the output clock.

Features

  • Ideal for OC-48/192 data clock
  • Integrated SAW (surface acoustic wave) delay line
  • VCSO frequency from 300 to 700MHz (Specify VCSO center frequency at time of order)
  • Low phase jitter of
  • Pin-selectable configuration
  • The M2004-12 adds Hitless Switching with Phase Build-out (HS/PBO) to ensure SONET/SDH MTIE and TDEV compliance during reference clock reselection
  • Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
  • Industrial temperature available
  • Single 3.3V power supply
  • Small 9 x 9 mm SMT (surface mount) package

Comparison

Applications

Documentation

Type Title Date
Product Change Notice PDF 361 KB
End Of Life Notice PDF 71 KB
2 items

Design & Development

Models