概览

简介

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation

特性

  • DDR3-800/1066/1333/1600/1866/2133 rate
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
  • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
  • Supports LVCMOS switching levels on the RESET and MIRROR inputs
  • Checks priority on DIMM-independent data inputs
  • Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through
  • Supports CKE Power Down operation modes
  • Supports Quad Chip Select operation features
  • RESET input disables differential input receivers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
  • Provides access to internal control words for configuring the device features and adapting in different RDIMM and   system applications
  • Latch-up performance exceeds 100mA
  • ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)

产品对比

应用

文档

类型 文档标题 日期
数据手册 PDF 2.42 MB
End Of Life Notice PDF 1.11 MB
概览 PDF 515 KB
产品变更通告 PDF 27 KB
产品变更通告 PDF 33 KB
5 items

设计和开发

模型