The 874003-02 is a high performance Differential-to- LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874003-02 has a bandwidth of 400kHz which is designed to provide good jitter attenuation. The 874003-02 uses IDT's 3RD Generation Femtoclock® PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.


  • Three Differential LVDS output pairs
  • One Differential clock input
  • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Output frequency range: 98MHz - 320MHz
  • Input frequency range: 98MHz - 128MHz
  • VCO range: 490MHz - 640MHz
  • Cycle-to-cycle jitter: 35ps (maximum)
  • For PCI-Express Spread-Spectrum Clocking support use the ICS874003-05
  • The 400kHz bandwidth mode allows the system
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages


文档标题 language 类型 文档格式 文件大小 日期
star 874003-02 DATASHEET 数据手册 PDF 868 KB
Errata# NEN-10-06 数据手册勘误表 PDF 115 KB
应用指南 & 白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products 应用文档 PDF 108 KB
PDN# : TP-20-05(R1) Revised PDN - Change Replacement for 85411AMLF(T) from 5PB1102CMGI(8) to 8SLVP1102ANLGI(8) 产品停产通告 PDF 743 KB
PDN# : TP-20-05 End-of-Life (EOL) Process on Select Part Numbers 产品停产通告 PDF 715 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB