NOTICE - The following device(s) are recommended alternatives:

The 85222-01 is a Dual LVCMOS / LVTTL-to- Differential HSTL translator. The 85222-01 has two single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.

特性

  • Two differential HSTL outputs
  • CLK0, CLK1 LVCMOS/LVTTL clock inputs
  • CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 350MHz
  • Part-to-part skew: 375ps (maximum)
  • Propagation delay: 1075ps (maximum)
  • VOH: 1.4V (maximum)
  • Full 3.3V and 2.5V operating supply voltage
  • 0°C to 70°C ambient operating temperature
  • Industrial temperature information available upon request
  • Available in lead-free RoHS-compliant package

产品选择

下单器件型号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
85222AM-01LF
Obsolete SOIC 8 C 是的 Tube
Availability
85222AM-01LFT
Obsolete SOIC 8 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
85222-01 Datasheet 数据手册 PDF 282 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-15-03 Quarter PDN for Declined Market 产品停产通告 PDF 542 KB
PCN# : A1309-01 Changed of Traceability Mark Format 产品变更通告 PDF 439 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
下载
85222-01 IBIS Model 模型 - IBIS ZIP 6 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB