The 9ZXL1950D is a second-generation, enhanced-performance DB1900Z-derivative differential buffer. The part is a pin-compatible upgrade to the 9ZXL1950B, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications.

特性

  • LP-HCSL outputs with 85Ω Zout; eliminate 76 resistors, save 130mm² of area
  • PCIe Gen 1–5 compliance
  • SMBus OE bits; software control of each output
  • 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 10 x 10 mm 72-VFQFPN package; small board footprint

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZXL1950DKILF
Package Info
 Active VFQFPN 72 I 是的 Tray
Availability

Buy / Quote
9ZXL1950DKILFT
Package Info
 Active VFQFPN 72 I 是的 Reel
Availability
Buy / Quote

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9ZXL15x0D-9ZXL19x0D-9ZXL1951D Family Datasheet – 数据手册 PDF 524 KB
应用指南 &白皮书
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 – 应用文档 PDF 244 KB
AN-975 Cascading PLLs – 应用文档 PDF 255 KB
AN-828 Termination - LVPECL – 应用文档 PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs – 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – 应用文档 PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers – 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection – 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations – 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter – 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units – 应用文档 PDF 565 KB
AN-808 PCI Express/HCSL Termination – 应用文档 PDF 137 KB
AN-805 Recommended Ferrite Beads – 应用文档 PDF 121 KB
PCN / PDN
PCN# : TP1910-03-R1 Update the Cut-off Date Code – 产品变更通告 PDF 163 KB
PCN# : TP1910-03 Top Metal Change – 产品变更通告 PDF 158 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – 产品变更通告 PDF 983 KB
下载
9ZXL1950D IBIS Model – 模型 - IBIS ZIP 28 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
PCI Express Timing Solutions Overview – 概览 PDF 275 KB
9ZXL1950 Schematic – 原理图 PDF 79 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
info: For device-specific or order-specific documentation, submit a support request.

开发板与套件

器件号 文档标题 类型 Company
EVK9ZXL1951D Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI 评估 Renesas

新闻及更多资源

类型 日期
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 博客 2018年5月21日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 新闻中心 2018年4月30日
An Insider’s Guide to Finding the Right Timing Device for Your System 博客 2017年12月18日
Why Fanout Buffers Make More Sense 博客 2017年11月28日
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped 新闻中心 2014年12月18日