The 9FGV0841 is an 8-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo=100 Ω. The device has 8 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

特性

  • PCIe Gen1–4 compliant
  • Integrated terminations provide 100Ω differential Zo: reduced component count and board space
  • 1.8V operation: reduced power consumption
  • Outputs can optionally be supplied from any voltage between 1.05V and 1.8V: maximum power savings
  • OE# pins: support DIF power management
  • LP-HCSL differential clock outputs: reduced power and board space
  • Programmable slew rate for each output: allows tuning for various line lengths
  • Programmable output amplitude: allows tuning for various application environments
  • DIF outputs blocked until PLL is locked: clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs: reduces EMI
  • External 25MHz crystal; supports tight ppm with 0ppm synthesis error
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control
  • 3.3V tolerant SMBus interface works with legacy controllers
  • Space-saving 6 × 6 mm 48-VFQFPN; minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment
  • Available in AEC-Q100 qualified, Grade 2 (-40°C to +105°C) version (wettable flank package)

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 48 I 是的 Tray
Availability
Active VFQFPN 48 I 是的 Reel
Availability
Active VFQFPN 48 C 是的 Tray
Availability
Active VFQFPN 48 C 是的 Reel
Availability
Active VFQFPN 48 2 是的 Tray
Availability
Active VFQFPN 48 2 是的 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 9FGV0841 Datasheet 数据手册 PDF 439 KB
使用指南与说明
Timing Products for NXP (Freescale) i.MX (Chinese) English 指南 PDF 512 KB
9FGx08 PCIe Clock Generator Evaluation Boards User Guide 手册 - 硬件 PDF 838 KB
应用指南 & 白皮书
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-918 Programmable Clocks vs Crystal Oscillators 应用文档 PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL 应用文档 PDF 235 KB
AN-843 PCI Express Reference Clock Requirements 应用文档 PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 产品变更通告 PDF 583 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : TB1311-01 New Carrier Tape on VFQFPN-28, VFQFPN-40, VFQFPN-48 产品变更通告 PDF 790 KB
其他
PCI Express Timing Solutions Overview 概览 PDF 275 KB
9FGV0841 Reference Schematic 原理图 PDF 79 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB

file_download下载

文档标题 language 类型 文档格式 文件大小 日期
模型
9FGV0841 IBIS Model 模型 - IBIS ZIP 97 KB