概要

説明

The 894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retimed data signals.

特長

  • Clock recovery for STM-4 (OC-12/STS-12) and
  • STM-1 (OC-3/STS-3)
  • Input: NRZ data (622.08 or 155.52 Mbit/s)
  • Output: clock signal (622.08MHz or 155.52MHz) and retimed
  • data signal at 622.08 or 155.52 Mbit/s
  • Internal PLL for clock generation and clock recovery
  • Differential inputs can accept LVPECL levels
  • Differential LVPECL data and clock outputs
  • Lock reference input and PLL lock output
  • 19.44MHz reference clock input
  • Full 3.3V supply mode
  • -40°C to 85°C operating temperature
  • Available in lead-free (RoHS 6) package
  • See ICS894D115I for a clock/data recovery circuit with a
  • TSSOP EPAD package
  • See ICS894D115I-04 for a clock/data recovery circuit with
  • LVDS outputs

製品比較

アプリケーション

ドキュメント

設計・開発

モデル