Overview
The SH7786 is a dual-core processor built around a pair of SH-4A CPUs for superior processing performance of up to 1920 MIPS (when operating at 533 MHz).
The two SH-4A cores employ a new multicore architecture that supports both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP), allowing the customer to choose whichever best matches the system under development. In addition, the clock frequency and powerdown (low-power) mode can be set independently for each CPU, so power consumption can be minimized while acommodating variations in the processing load. Finally, multiple PCI Express bus interfaces enable high-speed data transfer.
System Block Diagram
Specification
| Item | SH7786 Specifications |
|---|---|
| Product No. | R8A77860NBGV, R8A77860DBGV |
| Max. operating frequency | 1.25 V (internal), 1.5 V (DDR3-SDRAM, PCI Express), 3.3 V (I/O, PCI Express) |
| Max. processing performance | 533 MHz |
| Max. processing performance | 1,920 MIPS, 7.46 GFLOPS (operating at 533 MHz) |
| CPU cores | SH-4A × 2 |
| On-chip RAM | High-speed RAM: (8 Kbytes + 16 Kbytes) × 2 |
| Cache memory | 4-way set associative type, with separate 32 Kbytes for instructions and 32 Kbytes for data × 2, cache coherency support |
| L2 cache | 256 Kbytes |
| External memory and external bus interfaces |
DDR3-SDRAM memory controller:
|
| Main on-chip peripheral functions |
USB 2.0 host/function interface Ethernet controller (IEEE 802.3u compliant MII interface (no PHY)) SD host interface × 2 channels (max.) Display unit, 854 × 480 pixels (max.) Direct memory access controller × 24 channels Serial communication interface × 6 channels (max.) I2C interface × 2 channels Timer × 12 channels Sound interfaces Interrupt controller NAND flash memory controller × 1 channel (max.) On-chip debug function |
| Power-down modes |
Sleep mode Light sleep mode Module standby function |
| Package | 593-pin BGA (25 mm × 25 mm, 0.8 mm pitch) |
