OVERVIEW
The ISL6548A provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQ
during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ
/2) high current VTT
voltage without the need for a negative supply. A second PWM controller, which requires external MOSFET drivers, is available for regulation of the GMCH Core voltage. A sink/source LDO controller is also integrated for the CPU/GMCH VTT
termination voltage regulation. Another LDO is available for the ICH7 voltage.
The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU VTT termination voltage is within spec and operational.
All outputs, except VICH7 , have undervoltage protection. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated.
The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltagemode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ±2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH and CPU VTT termination voltage is within spec and operational.
All outputs, except VICH7 , have undervoltage protection. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated.
KEY FEATURES
- Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference for DDR VTT
- PWM Regulator for GMCH Core
- Sink/Source LDO Regulator for CPU/GMCH VTT Termination
- LDO Regulator for ICH7
- ACPI compliant sleep state control
- Glitch-free Transitions During State Changes
- VDDQ PWM Controller Drives Low Cost N-Channel MOSFETs
- 250kHz Constant Frequency Operation
- Both PWM controllers are Phase Shifted 180°
- Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
- Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications
- Simple Single-Loop Voltage-Mode PWM Control Design
- Fast PWM Converter Transient Response
- Under and Overvoltage Monitoring
- OCP on the VDDQ Switching Regulator
- Integrated Thermal Shutdown Protection
- Pb-Free Plus Anneal Available (RoHS Compliant)
BLOCK DIAGRAM
PARAMETRICS
Parameters
ISL6548A
Basic Information
Production Status
Mass Production
# of Outputs
5
Input Voltage Min (V)
4.5
Input Voltage Max (V)
5.5
Output Voltage Min (V)
0.8
Output Voltage 1 Max (V)
5.5
Output Current 1 Max (A)
25
Switching Frequency (kHz)
250
Bias Voltage (VCC) (V)
5
Output Voltage 2 Max (V)
2.75
Output Voltage 3 Max (V)
Adj.
Output Voltage 4 Max (V)
Adj.
Output Voltage 5 Max (V)
Adj.
Linear Output
Yes
DDR Capable
Yes
Qualification Level
Standard
Bias Voltage Range (V)
5
Temperature Range
0 to +70
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