The V850ES/SA2 and V850ES/SA3 are 32-bit single-chip microcontrollers that employ the V850ES CPU core and integrate peripheral functions such as ROM/RAM, timers/counters, serial interfaces, an A/D converter, a D/A converter, and a DMA controller.


Key Features:

  • Operating Voltage: 2.2 V to 2.7 V
  • Max. frequency: 20 MHz
  • ROM capacities: 128 to 256 KB mask ROM and 256 KB flash memory
  • RAM capacities: 8 to 16 KB
  • Package: 100-pin plastic TQFP, 121-pin plastic FBGA package
  • Number of instructions 83
  • Minimum instruction execution time:
    • 50 ns: Main clock = 20 MHz (μPD703200, 703201, 70F3201, 703204, 70F3204)
    • 59 ns: Main clock = 17 MHz (μPD703200Y, 703201Y, 70F3201Y, 703204Y, 70F3204Y)
    • 30.5 μs: Subclock = 32.768 kHz
  • General-purpose registers 32 bits x 32 registers
  • Instruction set
    • Signed multiplication (16 x 16 -> 32): 1 to 2 clocks
    • Signed multiplication (32 x 32 -> 64): 1 to 5 clocks
    • Saturated operation (with overflow/underflow detection function)
    • 32-bit shift instruction: 1 clock
    • Bit manipulation instruction
    • Load/store instruction with long/short format
  • Memory space:
    • 64 MB linear address space (for program/data)
    • Programmable wait function
    • Idle state insertion function
  • External bus interface
    • Multiplexed bus/separate bus output selectable
    • 8/16-bit data bus sizing function
    • 4-space chip select function
    • Wait functions (Programmable wait function, External wait function)
    • Idle state function
    • Bus hold function
  • Interrupts/exceptions:
    • External interrupts: 8 sources
    • Internal interrupts: 30 sources (μPD703200, 703201, 70F3201), 31 sources (μPD703200Y, 703201Y, 70F3201Y, 703204, 70F3204), 32 sources (μPD703204Y, 70F3204Y)
    • Software exception: 32 sources
    • Exception trap: 1 source
  • I/O ports:
    • V850ES/SA2: 82 (input ports: 14, I/O ports: 68)
    • V850ES/SA3: 102 (input ports: 18, I/O ports: 84)
    • 16-bit timer/event counter: 2 channels (PWM output)
    • 8-bit timer/event counter: 4 channels (connectable in cascade)
    • Real-time counter (for watch) Subclock/main clock operation: 1 channel
    • Dedicated on-chip hardware counter for weeks, days, hours, minutes, and seconds, Up to 4,095 weeks can be counted
    • Watchdog timer: 1 channel
  • Serial interface:
    • Asynchronous serial interface (UART)
    • Clocked serial interface (CSI)
    • I2C bus interface (I2C) (μPD703200Y, 703201Y, 70F3201Y, 703204Y, 70F3204Y only)
    • CSI/UART: 1 channel
    • UART: 1 channel
    • CSI/I2C: 1 channel
    • CSI : 2 channels (V850ES/SA2) / 3 channels (V850ES/SA3)
  • A/D converter 10-bit resolution: 12 to 16 channels
  • D/A converter 8-bit resolution: 2 channels
  • DMA controller: 4 channels (transfer object: Internal memory, on-chip peripheral I/O, and external memory)
  • ROM correction: 4 places specifiable
  • Clock generator: - Main clock/subclock operation - CPU clock: 7 steps (fX, fX/2, fX/4, fX/8, fX/16, fX/32, fXT)
  • Power save function HALT/IDLE/STOP mode


Below you will find information to support the development of your application.
You can find technical updates and datasheets for this product here.
You can find an explanation of orderable part numbers here.

Resources for Software and Hardware

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Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)


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