Overview

Description

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.

Features

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

Comparison

Applications

Documentation

Type Title Date
Datasheet PDF 568 KB
Product Change Notice PDF 31 KB
End Of Life Notice PDF 542 KB
3 items

Design & Development

Models