Overview

Description

The 723624 is a CMOS bidirectional synchronous (clocked) FIFO. Two independent 256 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

Features

  • Clock frequencies up to 83 MHz (8 ns access time)
  • Two independent clocked FIFOs buffering data in opposite directions
  • Programmable Almost-Empty and Almost-Full flags
  • Serial or parallel programming of partial flags
  • Port B bus sizing of 36-bits (long word), 18-bits (word) and 9-bits (byte)
  • Big- or Little-Endian format for word and byte bus sizes
  • Mailbox bypass registers for each FIFO
  • Free-running CLKA and CLKB may be asynchronous or coincident
  • Auto power down minimizes power dissipation
  • Available 128-pin TQFP package
  • Industrial temperature range (–40C to +85C) is available

Documentation

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PDF240 KB
Datasheet
PDF645 KB
End Of Life Notice
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End Of Life Notice
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Guide
PDF567 KB
Product Change Notice
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Product Change Notice

Design & Development

Software & Tools

Software Downloads

Title Type Date
PDF645 KB
End Of Life Notice
PDF86 KB
End Of Life Notice
PDF30 KB
End Of Life Notice

Models

Models

Title Type Date
ZIP11 KB
Model - IBIS
Model - SPICE

Support