UPD60510BF1-HN4-M1-A

Recommended Product
UPD60510BF1-HN4-M1-A
Production Status
Mass Production

BLOCK DIAGRAM

R-IN32 Block Diagram

PARAMETRICS

Parameters
UPD60510BF1-HN4-M1-A
Basic Information
Production Status
Mass Production
PLP
PLP (Refer to Orderable Parts)
Bit Size
32
Family
R-IN
Series
R-IN32M3
Group
R-IN32
Program Memory (KB)
768
RAM (KB)
512
Program Memory Type
ROMless
Pin Count
324
CPU
Cortex-M3
Max. Freq (MHz)
100
On-chip Oscillator
YES
On-chip Oscillator Freq. (MHz)
100
PLL
YES
DMA
YES
DMA Remarks
DMAC x 4 ch
External Interrupt Pins
29
I/O Ports
96
32-bit Timer (ch)
1
Watchdog Timer (ch)
1
CAN (ch)
2
Ethernet
YES
Ethernet Remarks
2ch
USB Endpoints
0
Clocked Serial Interface (ch)
2
UART (ch)
2
I2C (ch)
2
Operating Voltage Max (V)
1.1
Operating Voltage Min (V)
0.9
Power Supply
"VDD = 0.9 to 1.1 V, VDDIO = 3.0 to 3.6V"
Operating Temperature Max (°C)
85
Operating Temperature Min (°C)
-40
Remarks
"Industrial communication, include CC-Link IE Field slave IP"

Resources for Software and Hardware

Title Description
My Renesas Create a My Renesas account to use our tool download services, receive e-newsletter/update notifications, and take advantage of our other services.
e-learning Information for studying and learning about microcontrollers and microprocessors.
FAQ Frequently asked questions and useful hints for development.
Forum A forum and community site to share technical information, questions and opinions with others who use Renesas products.

Hardware Design Support

Title Description
IBIS/BSDL

IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.

BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.

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