The 8735BI-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL clock generator. The CLK, nCLK pair can accept most standard differential input levels. The 8735BI-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
Features
One differential 3.3V LVPECL output pair, one differential feedback output pair
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
External feedback for “zero delay” clock regeneration with configurable frequencies
Cycle-to-cycle jitter: 50ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in RoHS compliant package
Comparison
Applications
Documentation
Design & Development
Models
ECAD Models
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