Overview

The 83940D is a low skew, 1-to-18 LVPECL-to- LVCMOS/LVTTL Fanout Buffer. The 83940D has two selectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The 83940D is characterized at full 3.3V and 2.5V or mixed3.3V core, 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 83940D ideal for those clock distribution applications demanding well defined performance and repeatability.

83940D - Block Diagram
83940D - Pinout
83940D - Block Diagram
83940D - Pinout
  • 18 LVCMOS/LVTTL outputs
  • Selectable LVCMOS_CLK or LVPECL clock inputs
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
  • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 250MHz
  • Output skew: 150ps (maximum)
  • Part to part skew: 750ps (maximum)
  • Additive phase jitter, RMS: < 0.03ps (typical)
  • Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output supply modes
  • 0°C to 70°C ambient operating temperature
  • Lead-Free package available

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    83940DYLF
    circleObsolete
    memory
    view_in_ar
    		TQFP 32 C Yes Tray
    83940DYLFT
    circleObsolete
    memory
    view_in_ar
    		TQFP 32 C Yes Reel
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