The PCIe data channel is a high speed serial communication interface with speeds up to 8 GT/s, increasing to 32 GT/s with PCIe Gen5 devices. As with any serial communication interface, the most critical clock parameter is phase jitter. This makes PCIe clock generators the heart of PCIe timing and the gating factor in system performance and reliability. A PCIe-based system with a lower-performance clock may completely fail to train. More insidiously, the link may train to less than the advertised throughput, or will experience many link errors thus requiring data be resent. These last two items are insidious because while the system will function, performance will be degraded due to the reduced link bandwidth.
Renesas PCIe clock generators (reference clocks) provide 1 to 8 outputs, exceeding the published PCIe specifications at each performance node, Gen 1, Gen 2, Gen 3, Gen 4 and Gen 5. Renesas also offers these high performance clock generators in 1.5V, 1.8V or 3.3V versions, allowing the designer to power their PCIe clock generators from the same power supply as their FPGA or System on a Chip (SoC). The Renesas PCIe reference clocks are offered with integrated terminations to allow direct connection of the outputs to the transmission line, thus saving significant board space.
Download: PCIe Reference Clock Jitter Measurements for Gen5 and Beyond (PDF)
Download: PCI Express Timing Solutions Overview (PDF)