An application such as a handheld ultrasound requires complex clocking for a central FPGA, SoC and ASIC. Renesas's VersaClock® 6E family of products offers a wide range of I/O configurations allowing customers to ‘right-size’ the clock to their design, resulting in the smallest footprint device for the application. Our wide range of buffers allows for clock fanouts with minimal additive jitter while supporting customers.
|Timing CommanderTiming Commander™ is an innovative Windows™-based software platform enabling system design engineers to configure, program, and monitor sophisticated timing devices with an intuitive and flexible graphical user interface (GUI).||Code Generator||Renesas|
|Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility||Blog Post||Jun 14, 2019|
|An Insider’s Guide to Finding the Right Timing Device for Your System||Blog Post||Dec 19, 2017|