With the exploding number of “things” connected to the internet and the real-time feedback requirements of these devices, demands for network systems with much higher speeds are growing bigger year after year. As the industry migrates to 100Gb traffic, high power consumption of traditional search engine solutions becomes a huge problem for data center networks. Renesas offers a low power search solution for higher packet forwarding that grows with your network.

The Renesas Exact Match reference design includes a proprietary search algorithm, LLDRAM-III control IP on an FPGA host controller, and is accompanied by a suite of development tools.

Exact Match Reference Design Key Features

  • Lookup over one million rules of packet headers for a 100Gb network system in around 2 watts, which means the quantity of required memory devices is reduced to 1/15th and memory power consumption is cut by 60%.*
  • Scale with future network protocols with flexible configuration of the search key length of up to 575 bits.
  • Reduce the development cycle time of network systems by providing an all-in-one development platform with an on-board Xilinx FPGA and LLDRAM-III

*If MAC address lookup at 150 million search per second

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Packet Header Search Solution (100G) Block Diagram

Related Products

Product ID Title Featured Document
DRAMs
RMHE41A364AGBG-120 1.1G-BIT Low Latency DRAM-III Common I/O Burst Length of 4 Datasheet

Evaluation System

Improve time-to-market by utilizing proven evaluation system for product development

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Packet Header Search Solution (100G) Evaluation System

Evaluation system includes:

  • Reference board with onboard FPGA and LLDRAM III
  • Sample design with Search Engine IP
  • Verification and evaluation applications

Item List for Evaluation System

Items Content
Documents Quick Start Guide, Exact Match Search IP Design Guide, PCB Design Guide, GUI Software Guide, API Guide, LLDRAM-III data sheet
Exact Match Search IP (as a reference design) Verilog Source Code, AXI4 Slave Bridge Module
LLDRAM-III model Verilog Behavior Model, IBIS Model
Sample design Verilog Source Code, FPGA Implementation Environment, Logic Simulation Environment (VCS /Modelsim), GUI Software
API for table maintenance ANSI-C Source Code
Reference board Interoperability verified between FPGA and LLDRAM-III

To inquire about this Renesas evaluation system, please contact us here.

Documentation & Downloads

Title Other Languages Type Format File Size Date
Other
LLDRAM-Ⅲ Exact Match Search Solution 日本語 Others PDF 766 KB
LLDRAM-Ⅲ Control IP Solution 日本語 Others PDF 793 KB