Overview

The CD4023BMS is a triple 3-input CMOS NAND gate that provides the system designer with direct implementation of the NAND function and supplements the existing family of CMOS gates. All inputs and outputs are buffered. The CD4023BMS is supplied in these 14-lead outline packages: Braze Seal DIP H4Q, Frit Seal DIP H1B and a Ceramic Flatpack H3W.

CD4023BMS Functional Diagram
CD4023BMS Functional Diagram
  • High-voltage types (20V rating)
  • Propagation delay time = 60ns (typ.) at CL = 50pF, VDD = 10V
  • Buffered inputs and outputs
  • Standardized symmetrical output characteristics
  • Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
  • 100% tested for maximum quiescent current at 20V
  • 5V, 10V and 15V parametric ratings
  • Noise margin (over full package temperature range):
    • 1V at VDD = 5V
    • 2V at VDD = 10V
    • 2.5V at VDD = 15V
  • Meets all requirements of JEDEC tentative standards No. 13B, "Standard Specifications for Description of "B" Series CMOS devices

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Carrier Type
    MOQ
    DLA SMD
    Buy / Sample
    Part Number
    CD4023BDMSR
    circleObsolete
    memory
    view_in_ar
    		SBDIP Tube 25 5962R9662103VCC
    CD4023BHSR
    circleLast Time Buy
    memory
    view_in_ar
    Samples Available
    		 Die Waffle Pack 100 5962R9662103V9A Get Samples,
    CD4023BKMSR
    circleObsolete
    memory
    view_in_ar
    		CFP Tray 25 5962R9662103VXC
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