Overview
Description
The 74FCT162511T 16-bit high-speed, low-power registered/latched transceiver with parity combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The device has a parity generator/ checker in the A-to-B direction and a parity checker in the B-to-A direction. The 74FCT162511T operates at -40C to +85C
Features
- A and C speed
- Typical tsk(o) (Output Skew) 250ps, clocked mode
- Low input and output leakage ?1 uA (max)
- ESD > 2000V per MIL-STD-883, Method 3015
- > 200V using machine model (C = 200pF, R = 0)
- VCC = 5V ±10%
- Balanced Output Drivers: ±24mA
- Series current limiting resistors
- Generate/Check, Check/Check modes
- Open drain parity error allows wire-OR
- Available in 56 pin SSOP and TSSOP packages
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| TSSOP | 56 | C | Yes | Tube | ||
| TSSOP | 56 | C | Yes | Reel | ||
| SSOP | 56 | C | Yes | Tube | ||
| SSOP | 56 | C | Yes | Reel | ||
| TSSOP | 56 | C | Yes | Tube | ||
| TSSOP | 56 | C | Yes | Reel | ||
| SSOP | 56 | C | Yes | Tube | ||
| SSOP | 56 | C | Yes | Reel |
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