Overview
Description
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, and 667MHz.
Features
- 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on CSR and RESET inputs
- Low voltage operation VDD = 1.7V to 1.9V
Comparison
Applications
Documentation
= Featured Documentation
Log in required to subscribe
|
|
|
---|---|---|
Type | Title | Date |
Datasheet | PDF 662 KB | |
1 item
|
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.