Renesas Electronics Corporation
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M2004-01

Obsolete

Frequency Translation PLL

Overview

The M2004 variants -01 and -11 are Voltage Controlled SAW Oscillator (VCSO) based clock generator PLLs designed for clock frequency translation and jitter attenuation in a high-speed data communications system. The clock multiplication ratio and output divider ratio are pin-selectable and also configurable through serial programming. External loop components allow the tailoring of PLL loop response. The M2004-11 adds Hitless Switching with Phase Build-out (HS/PBO) to ensure that reference clock reselection does not disrupt the output clock.

m2004-01 - Block Diagram
m2004-01 - Pinout
m2004-01 - Block Diagram
m2004-01 - Pinout
  • Ideal for OC-48/192 data clock
  • Integrated SAW (surface acoustic wave) delay line
  • VCSO frequency from 300MHz to 700MHz (Specify VCSO center frequency at time of order)
  • Low phase jitter of < 0.5ps RMS, typical (12kHz to 20MHz or 50kHz to 80MHz)
  • Pin-selectable or serially programmed configuration
  • The M2004-11 adds Hitless Switching with Phase Build-out (HS/PBO) to ensure SONET/SDH MTIE and TDEV compliance during reference clock reselection
  • Reference clock inputs support single-ended LVCMOS, LVTTL
  • Industrial temperature available
  • Single 3.3V power supply
  • Small 9mm x 9mm SMT (surface mount) package

Documentation

Type Title Date
Product Change Notice
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products
PDF 361 KB
End Of Life Notice
PDN# : Z-13-01 PRODUCT DISCONTINUANCE NOTICE
PDF 71 KB
2 items

Design & Development

ECAD Models

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