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Overview

Description

Low skew, low jitter PLL clock driver. 1 to 10 differential clock distribution (SSTL_18)

Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

Comparison

Applications

Documentation

Type Title Date
Datasheet PDF 282 KB
End Of Life Notice PDF 549 KB
End Of Life Notice PDF 545 KB
End Of Life Notice PDF 544 KB
Product Change Notice PDF 252 KB
Product Change Notice PDF 194 KB
Product Change Notice PDF 99 KB
Product Change Notice PDF 1.11 MB
8 items

Design & Development

Models

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Diagram of ECAD Models