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74SSTUBF32869A

Obsolete

14-Bit Configurable Registered Buffer for DDR2

74SSTUBF32869A Datasheet

Overview

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

  • 14-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • 50% more dynamic driver strength than standard SSTU32864
  • Supports LVCMOS switching levels on C1 and RESET# inputs
  • Low voltage operation

Documentation

Featured Documentation
Type Title Date
Datasheet
74SSTUBF32869A Datasheet
PDF 493 KB
End Of Life Notice
PDN# : CQ-20-05 End-of-Life (EOL) Process on Select Part Numbers
PDF 720 KB
Product Change Notice
PCN#: A1309-03 Additional Assembly Sources
PDF 398 KB
3 items

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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