Overview
Description
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.
Features
- 28-bit 1:2 registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on CSGateEN and RESET inputs
- Low voltage operation: VDD = 1.7V to 1.9V
Comparison
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 492 KB | |
| End Of Life Notice | PDF 783 KB | |
| Product Change Notice | PDF 31 KB | |
3 items
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| CABGA | 160 | C | No | Tray | ||
| CABGA | 160 | C | No | Reel | ||
| CABGA | 160 | C | Yes | Tray | ||
| CABGA | 160 | C | Yes | Reel |
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