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SH7786

Overview

The SH7786 is a dual-core processor built around a pair of SH-4A CPUs for superior processing performance of up to 1920MIPS (when operating at 533MHz).
The two SH-4A cores employ a new multicore architecture that supports both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP), allowing the customer to choose whichever best matches the system under development. In addition, the clock frequency and powerdown (low-power) mode can be set independently for each CPU, so power consumption can be minimized while acommodating variations in the processing load. Finally, multiple PCI Express bus interfaces enable high-speed data transfer.

System Block Diagram

Specifications

SH7786 Group

ItemSH7786 Specifications
Product No.R8A77860NBGV, R8A77860DBGV
Max. operating frequency1.25 V (internal), 1.5 V (DDR3-SDRAM, PCI Express), 3.3 V (I/O, PCI Express)
Max. processing performance533 MHz
Max. processing performance1,920 MIPS, 7.46 GFLOPS (operating at 533 MHz)
CPU coresSH-4A × 2
On-chip RAMHigh-speed RAM: (8 Kbytes + 16 Kbytes) × 2
Cache memory4-way set associative type, with separate 32 Kbytes for instructions and 32 Kbytes for data × 2, cache coherency support
L2 cache256 Kbytes
External memory and external bus interfaces
  • DDR3-SDRAM memory controller:
    Supports connection of DDR3-SDRAM via 32-bit bus.
    Max. operating frequency: 533 MHz
  • Local bus state controller:
    Supports connection of SRAM, burst ROM, etc.
    Selectable bus width of 8, 16, 32, or 64 bits
  • PCI Express bus controller:
    Operates as PCIe root point or end point.
    Multi-lane (4/2/1) support
    <support for "4 lane plus 1 lane" or "2 lane plus 1 lane plus 1 lane">
  • Support for 1 virtual channel
Main on-chip peripheral
functions
  • USB 2.0 host/function interface
  • Ethernet controller (IEEE 802.3u compliant MII interface (no PHY))
  • SD host interface × 2 channels (max.)
  • Display unit, 854 × 480 pixels (max.)
  • Direct memory access controller × 24 channels
  • Serial communication interface × 6 channels (max.)
  • I 2 C interface × 2 channels
  • Timer × 12 channels
  • Sound interfaces
  • Interrupt controller
  • NAND flash memory controller × 1 channel (max.)
  • On-chip debug function
Power-down modes
  • Sleep mode
  • Light sleep mode
  • Module standby function
Package593-pin BGA (25 mm × 25 mm, 0.8 mm pitch)

 

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