The SH-Navi3 is a dual-core SoC built around a pair of SH-4A CPUs for superior processing performance of up to 1920MIPS (when operating at 533MHz).
It integrates graphics and image recognition processing functions that have been tweaked for improved performance.
Dual DDR3-SDRAM interfaces, which support simultaneous access, and a PCI Express interface enable ultra-high-speed data transfer. The many on-chip peripheral functions also include a serial ATA interface, allowing increased easy-to-use in car information terminal applications.
System Block Diagram
|Power supply voltage||1.25 V (internal)/3.3 V, 1.5 V (external)|
|Maximum operating frequency||533 MHz|
|Processing performance||1,920 MIPS, 7.46 GFLOPS (at 533 MHz)|
|CPU core||SH-4A core × 2|
|On-chip RAM||ILRAM: 8 Kbytes + OLRAM: 16 Kbytes|
Divided into 32 Kbytes instruction/32 Kbytes data × 2, 4-way set
associative type, cache coherency support
|L2 cache||128 Kbytes|
Support for connecting two channels of DDR3-SDRAM (DDR1066) modules via dedicated DDR3 bus with 16-bit bus width (Both channels of the dedicated bus can be accessed at the same time)
Max. operating frequency: 533 MHz
Support for direct connection of SRAM or ROM to expansion bus
|Extension bus||Address space: 64Mbytes × 6|
|Main on-chip peripheral functions||
|Package||653-pin BGA (25 mm × 25 mm)|